The present invention relates to cleaning compositions that can be used for a variety of applications including, for example, removing unwanted resist films, post-etch, and post-ash residue on a semiconductor substrate. In particular, the present invention relates to cleaning compositions useful for the removal of residue, preferably copper-containing post-etch and/or post-ash residue, from the surface of substrates, preferably microelectronic devices, and methods of using said compositions for removal of same.
The background of the present invention will be described in connection with its use in cleaning applications involving the manufacture of integrated circuits. It should be understood, however, that the use of the present invention has wider applicability as described hereinafter.
In the manufacture of integrated circuits, it is sometimes necessary to etch openings or other geometries in a thin film deposited or grown on the surface of silicon, gallium arsenide, glass, or other substrate located on an in-process integrated circuit wafer. Present methods for etching such a film require that the film be exposed to a chemical etching agent to remove portions of the film. The particular etching agent used to remove the portions of the film depends upon the nature of the film. In the case of an oxide film, for example, the etching agent may be hydrofluoric acid. In the case of a polysilicon film, it will typically be hydrofluoric acid or a mixture of nitric acid and acetic acid.
In order to assure that only desired portions of the film are removed, a photolithography process is used, through which a pattern in a computer drafted photo mask is transferred to the surface of the film. The mask serves to identify the areas of the film which are to be selectively removed. This pattern is formed with a photoresist material, which is a light sensitive material spun onto the in-process integrated circuit wafer in a thin film and exposed to high intensity radiation projected through the photo mask. The exposed or unexposed photoresist material, depending on its composition, is typically dissolved with developers, leaving a pattern which allows etching to take place in the selected areas, while preventing etching in other areas. Positive-type resists, for example, have been extensively used as masking materials to delineate patterns on a substrate that, when etching occurs, will become vias, trenches, contact holes, etc.
Increasingly, a dry etching process such as, for example, plasma etching, reactive ion etching, or ion milling is used to attack the photoresist-unprotected area of the substrate to form the vias, trenches, contact holes, etc. As a result of the plasma etching process, photoresist, etching gas and etched material by-products are deposited as residues around or on the sidewall of the etched openings on the substrate.
Such dry etching processes also typically render the resist mask extremely difficult to remove. For example, in complex semiconductor devices such as advanced DRAMS and logic devices with multiple layers of back end lines of interconnect wiring, reactive ion etching (RIE) is used to produce vias through the interlayer dielectric to provide contact between one level of silicon, silicide or metal wiring to the next level of wiring. These vias typically expose, Al, AlCu, Cu, Ti, TiN, Ta, TaN, silicon or a silicide such as, for example, a silicide of tungsten, titanium or cobalt. The RIE process, for example, leaves a residue on the involved substrate comprising a complex mixture that may include, for example, re-sputtered oxide material, polymeric material derived from the etch gas, and organic material from the resist used to delineate the vias.
Additionally, following the termination of the etching step, the photoresist and etch residues must be removed from the protected area of the wafer so that the final finishing operation can take place. This can be accomplished in a plasma “ashing” step by the use of suitable plasma ashing gases. This typically occurs at high temperatures, for example, above 200 degrees C. Ashing converts most of the organic residues to volatile species, but leaves behind on the substrate a predominantly inorganic residue. Such residue typically remains not only on the surface of the substrate, but also on the inside walls of vias that may be present. As a result, ash-treated substrates are often treated with a cleaning composition typically referred to as a “liquid stripping composition” to remove the highly adherent residue from the substrate. Finding a suitable cleaning composition for removal of this residue without adversely affecting, e.g., corroding, dissolving or dulling, the metal circuitry has also proven problematic. Failure to completely remove or neutralize the residue can result in discontinuances in the circuitry wiring and undesirable increases in electrical resistance.
Cleaning of post-etch residues remains a critical process step for any low-k dielectric material to succeed. As the dielectric constant of the low-k material pushes below 2.4, the chemical and mechanical sensitivity increases (e.g., chemical strength decreases, etc.), thereby requiring shorter process times and/or less aggressive chemistries. Unfortunately, shorter process times generally translates to more aggressive chemistries which can have a detrimental effect on the low-k dielectric material, as well as other stack materials (e.g., copper, etch stop, etc.).
Also, new uses for various metals are being developed that create challenges for removing their residues. One such example is the use of cobalt as an insulation of diffusion barrier layer layer to prevent the migration of copper into a wafer or dielectric layer. Cobalt-containing post-etch residue is very difficult to remove from, for example, via walls. Thus, improved cleaning chemistries with very high selectivity are desired.
Prior art stripping compositions include, for example: U.S. Pat. No. 7,399,356 (Aoyama), U.S. Pat. No. 6,755,989 (Wojtczak), U.S. Pat. No. 7,250,391 (Kanno), U.S. Pat. No. 7,723,280 (Brainard), U.S. patent application Publication No. 2006/0016785 (Egbe); U.S. patent application Publication No. 2006/0178282 (Suyama), U.S. patent application Publication No. 2006/0237392 (Auger), U.S. patent application Publication No. 2006/0270573 (Ikemoto), U.S. patent application Publication No. 2007/0078073 (Auger), and U.S. patent application Publication No. 2009/0301996 (Visintin). Such prior art stripping compositions for removing the etching residue suffer, however, from significant drawbacks. For example, their use tends to erode copper wire exposed on the bottoms of via holes. Moreover, where porous interlayer low-k dielectrics are concerned, prior art stripping compositions either etch the porous interlayer dielectric materials or include components that adsorb into the pores thus increasing the dilectric constant, k, of the dielectric materials, which may potentially negatively impact the performance of the ultimate device.
Therefore, there is a need in the art for a cleaning composition for back end of the line cleaning operations that effectively cleans substrates comprising porous interlayer dielectric layers, but does not significantly etch metals (e.g., Cu, Al) or the porous low-k dielectrics, and that does not significantly negatively impact the dielectric constant of the porous low-k films.